In a general circuit including transistors manufactured by using a Si wafer or SOI (silicon on insulator), as the operation voltage is reduced by progress of microfabrication, consumed power is reduced.
Consumed power is a sum of dynamic power and static power (hereinafter, also referred to as standby power): the dynamic power is power consumed mainly by charge and discharge of the gate capacitor of transistors and the parasitic capacitor formed with wirings connecting transistors and circuit blocks, and the like; the static power is power consumed when circuits do not operate.
As one of methods for reducing the consumed power, there is a technique called clock gating (for example, see Patent Document 1). Clock gating is a technique by which supply of a clock signal to a circuit is stopped in a period during which the circuit does not operate. By the method, the power consumed in parasitic capacitor of wirings supplied with a clock signal or the like can be reduced.